1. Field of the Invention
This invention relates to large magnetic core memories having a partial select current providing a total drive current at a selected core that rapidly increases to the coercive MMF of the core and then slowly increases toward the full drive current.
2. Discussion of the Prior Art
Magnetic core memories have long been used to store data for digital applications. They have been built in many different configurations, but the currently most popular configurations are a 3 wire-3 dimensional memory utilizing a double herringbone core pattern inductively coupled by orthogonal drive conductors and a sense-inhibit conductor pair and a 2 wire, 21/2 dimensional type of memory. Many improvements have been made to increase memory speed and to increase the number of cores for each sense-inhibit conductor pair, thereby decreasing memory costs. Core spacing has been decreased, core size has been decreased and core composition has been improved.
Currently, memories are being commercially manufactured with 16K or 32K (K=1024) 13 mil outside diameter cores coupled to each sense-inhibit conductor pair and 64K cores are being contemplated. However, the energy of a core switching signal is proportional to core volume and hence the small, thin 13 mil cores produce a very small amplitude short duration core output switching signal. While the signal energy is being decreased by smaller core sizes, the noise and signal propagation times are being increased as a result of the increasing number of cores on a sense-inhibit conductor pair. A small noise pulse, called delta noise, is generated by each partially selected core as the drive current is generated. The sense-inhibit conductors are arranged for partial cancellation, but delta noise varies slightly with memory state and other factors such as drive amplitude, drive duration, temperature and previous disturb history and complete cancellation is impossible. The uncancelled delta noise thus increases with the number of cores and approaches the switching signal in magnitude. These noise problems are exacerbated by the use of low drive cores, which tend to have smaller magnitude output switching pulses and less defined switching characteristics than high drive cores. They, of course, have the advantage of reducing power requirements.
FIG. 2 illustrates the criticality of distinguishing a core switching pulse from the noise signals. It illustrates typical worst case operating conditions in a memory having 16K 1370 Ampex Corporation cores per sense-inhibit conductor pair in a 3 wire-3 dimensional memory. The 1370 core is a temperature independent punched tape core having a 13 mil outside diameter and a nominal total drive current of 700 ma. It is a moderately high drive type of core.
Curves A and C represent respectively the switching and noise pulses at 10% high drive current at +110.degree. C. while curves b and d illustrate the switching and noise pulses at 10% low drive current at -60.degree. C. temperature. These are the worst case opposite extremes for this core. Commercially practical sense amplifiers require detection of a voltage signal during a minimum 25-30 nsec strobing interval with a selected voltage threshold greater than 8 millivolts.
As seen from FIG. 2, a mere 20 nsec strobing interval at a threshold of 10.0 mv barely fits within the worst case conditions. An inadequate time tolerance of 6 nsec exists on each side of the strobing interval to account for variations in switching signal propagation times along the sense conductors and the noise remains dangerously close to the threshold level as represented by curve C. Even though the current on the perpendicular conductor is delayed relative to the greater noise generating parallel current, the noise remains extremely high during the strobing interval. At the same time under the nominal conditions of curve B, the switching signal magnitude is barely above the threshold at the start of the strobing interval. Even the slightest variation in switching signal characteristics of a core will require the core to be replaced in the memory at great expense.
To meet the extremely tight core tolerances required by the prior art memory configuration represented by FIG. 2, it is necessary to subject the memory cores to 100% inspection. This inspection eliminates about one-half of the cores, thus doubling the bulk core costs. The handling required for inspection also creates mechanical damage, thus increasing the number of unacceptable cores, some of which may escape the inspection process and be wired into a memory. Once a memory is wired it must be thoroughly tested and any core that deviates from a narrow tolerance range in switching characteristics must be replaced. The longer sense lines of course increase the cost of rework and the additional handling required for rework inflicts additional damage upon the cores. Inspection and rework now account for more than half the cost of a core memory.